Bipolar junction transistor (BJT) for liquid flow biosensing applications without a reference electrode and large sensing area

ABSTRACT

A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

BACKGROUND Technical Field

The present invention generally relates to sensors, and moreparticularly to sensors including bipolar junction transistors.

Description of the Related Art

Mobile (portable and wearable) sensing technologies can non-invasivelymonitor health using bio-fluids such as sweat, saliva, urine have thepotential to provide cost effective and enhanced healthcare,particularly in the treatment of chronic diseases which places heavyburden on societies. To develop mobile sensing technology, sensors areneeded that can provide accurate data in a mobile setting. Hence,sensors may be desired to have robust and simple calibration, highsensitivity, low noise, low power requirements, miniaturized and can becost effectively mass produced.

SUMMARY

In accordance with an embodiment of the present disclosure, a bipolarjunction transistor (BJT) containing sensor is provided that includes avertically oriented stack of an emitter overlying a supportingsubstrate, a base region present directly atop the emitter and acollector atop the base region. A first extrinsic base region is incontact with a first sidewall of a vertically orientated base region.The first extrinsic base region is electrically contacted to provide thebias current of the bipolar junction transistor during sensor operation.A second extrinsic base region in contact with a second sidewall of thebase region, the second extrinsic base region including a sensingelement. The device may further include a sample trench having a trenchsidewall provided by the sensing element.

In another embodiment, the sensor may include a sensor composed of asample trench. The sensor further includes a first vertically orientatedbipolar junction transistor doped to a first conductivity type. Thefirst vertically bipolar junction transistor having a first sensingsurface of an extrinsic base region providing a first sidewall of thesample trench. A second vertically oriented bipolar junction transistordoped to a second conductivity type having a second sensing surface ofan extrinsic base region a second sidewall of the sample trench.

In yet another aspect, a method of forming a sensor is provided. Themethod of forming a sensor may include forming a bipolar junctiontransistor including a vertically oriented base region, and a twocomponent extrinsic base region. The method may further include forminga sensor surface on a sidewall of a first component of the extrinsicbase that is opposite a sidewall of the first component of the extrinsicbase that is in contact with the vertically oriented base region. Themethod may further include forming a sample trench having a sidewallprovide by the sensor surface.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description will provide details of preferred embodimentswith reference to the following figures wherein:

FIG. 1 is a side cross-sectional view depicting a bipolar junctiontransistor (BJT) containing sensor that includes a vertically orientedbase region, a portion of an extrinsic base region that includes asensing element, and a sample trench having a trench sidewall providedby the sensing element, in accordance with one embodiment of the presentdisclosure.

FIG. 2 is a top down view of the structure depicted in FIG. 1.

FIG. 3 is a side cross-sectional view of a bipolar junction transistor(BJT) containing sensor including a sample trench, in which the sensorfurther includes a first vertically oriented bipolar junction transistordoped to a first conductivity type having a first sensing surface of anextrinsic base region providing a first sidewall of the sample trench,and a second vertically oriented bipolar junction transistor doped to asecond conductivity type having a second sensing surface of an extrinsicbase region providing a second sidewall of the sample trench, inaccordance with another embodiment of the present disclosure.

FIG. 4 is a top down view of structure depicted in FIG. 3.

FIG. 5 is a top down view of a sensor including multiple BJT devicessensing along a sample trench.

FIG. 6 is top down view depicting a sensor for parallel sensing of asample within a sample reservoir using multiple BJT devices, inaccordance with one embodiment of the present disclosure.

FIG. 7 is a side cross-sectional view showing a semiconductor substratehaving compound semiconductor layers and dielectric layers thereon.

FIG. 8 is a side cross-sectional view depicting formation of a trench inthe structure depicted in FIG. 7, formation of an oxide layer within thetrench, and exposing a portion of an emitter layer.

FIG. 9 is a side cross-sectional view depicting epitaxially forming asemiconductor material in the trench of the structure depicted in FIG.8.

FIG. 10 is a side cross-sectional view depicting removal of asacrificial material from the structure shown in FIG. 9 to exposesidewalls of the vertically oriented base region.

FIG. 11 is a side cross-sectional view depicting epitaxial growth ofextrinsic base material on the base region.

FIG. 12 is a side cross-sectional view depicting patterning theepitaxially semiconductor material to provide the geometry of theextrinsic base region portions of the device, and depositing aninterlevel dielectric layer.

FIG. 13 is a side cross-sectional view of depicting forming a trenchthat exposes a portion of the vertically oriented base region.

FIG. 14 is a side cross-sectional view depicting following epitaxialgrowth of collector material within the trench depicted in FIG. 13, inaccordance with one embodiment of the present disclosure.

FIG. 15 is a side cross-sectional view deposition of an interlayerdielectric (ILD) layer on the structure depicted in FIG. 14, and forminga sample trench exposing a sidewall of an extrinsic base region portionof the device.

FIG. 16 is a side cross-sectional view depicting one embodiment of alateral etch process to laterally etching the extrinsic base region ofthe structure depicted in FIG. 15 forming an undercut region.

FIG. 17 is a side cross-sectional view of depositing at least one metalfilling the trench, as well as the undercut region, depicted in FIG. 16.

FIG. 18 is a side cross-sectional view depicting recessing a portion ofthe metal that is present within the trench, in accordance with oneembodiment of the present disclosure.

FIG. 19 is a side cross-sectional view depicting applying an anisotropicetch process to the recessed metal that is present within the trench,wherein the anisotropic etch process removes a majority of the metal,while a remainder of the metal is present in the undercut region toprovide the sensing element of the BJT sensor, in accordance with oneembodiment of the present disclosure.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosedherein; however, it is to be understood that the disclosed embodimentsare merely illustrative of the claimed structures and methods that maybe embodied in various forms. In addition, each of the examples given inconnection with the various embodiments is intended to be illustrative,and not restrictive. Further, the figures are not necessarily to scale,some features may be exaggerated to show details of particularcomponents. Therefore, specific structural and functional detailsdisclosed herein are not to be interpreted as limiting, but merely as arepresentative basis for teaching one skilled in the art to variouslyemploy the methods and structures of the present disclosure. Forpurposes of the description hereinafter, the terms “upper”, “lower”,“right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the embodiments of the disclosure,as it is oriented in the drawing figures. The terms “positioned on”means that a first element, such as a first structure, is present on asecond element, such as a second structure, wherein interveningelements, such as an interface structure, e.g. interface layer, may bepresent between the first element and the second element. The term“direct contact” means that a first element, such as a first structure,and a second element, such as a second structure, are connected withoutany intermediary conducting, insulating or semiconductor layers at theinterface of the two elements.

Mobile (portable and wearable) sensing technologies can non-invasivelymonitor health using bio-fluids such as sweat, saliva, urine have thepotential to provide cost effective and enhanced healthcare,particularly in the treatment of chronic diseases which places a heavyburden on societies. In some embodiments, bipolar junction transistors(BJT) sensors are better suited for mobile sensing applications than FETsensors because BJT sensors can have a simpler and more robustcalibration; sensitivity and signal to noise ratio (SNR) in BJT sensorscan be independent of applied voltages; and in BJT sensors it ispossible to have the sub-threshold swing (measure of sensitivity) be thesame for various devices. BJT sensors can also have a higher sensitivityand SNR in comparison to FET sensors.

The sensor structure and methods described herein employ a verticalbipolar transistor design having a large base area which is easilyaccessible from the sensing side to create a very large sensing area ascompared to prior art. Increasing the contact area to measuring solutionwill reduce the noise and increase SNR, and decrease response time. Insome embodiments, the design of the BJT sensors of the presentdisclosure provides a base contact on one side of the base, with theother side being free to measure the potential of the flowing solutionthat can be present in a sample trench. This leads to elimination ofreference electrode as used in prior devices. In some embodiments, thesample liquid being sensed by the BJT containing sensor will be pumpedand flow in a horizontal manner in a trench, where one or both sidewallof the trench are BJT sensing areas. In some embodiments, the methodsand structures provided herein can provide one, two or multiple BJT'salong a trench enabling measurements of multiple properties of DNA orproteins at the same time. Lowest noise for III-V BJT would be using anInP emitter (wider bandgap=lower noise), or for group IV basedsemiconductors a Si—SiGe—Si structure. The methods and structures of thepresent disclosure are now described with more detail with reference toFIGS. 1-19.

FIGS. 1 and 2 depicts a bipolar junction transistor (BJT) containingsensor that includes a vertically oriented base region 48, a portion ofan extrinsic base region 54 b that includes a sensing element, and asample trench 300 having a trench sidewall provided by the sensingelement 200. The extrinsic base region 54 a, 54 b includes two portions.The left portion, i.e., first portion 54 a, of the extrinsic base isphysically separate from the right portion, i.e. second portion 54 b, ofthe extrinsic base, and hence are not electrically connected. The firstportion 54 a of the extrinsic base region, i.e., base contact, can beused to set the bias current of the transistor during sensingoperations. The first portion 54 a of the extrinsic base region mayprovide the metal base contact. The second portion 54 b of the extrinsicbase portion, which is the side of the bipolar junction transistoradjacent to the sample trench 300, has a sensing surface. The secondportion 54 b of the extrinsic base portion is physically separate fromthe metal base contact. The sensing surface 200 may extends along anentire height H1 of the extrinsic base 54 a, 54 b. The sensing surface200 extends continuously along the entire height H1 of the extrinsicbase 54 a, 54 b and can have a uniform width without any breaks incontinuity.

The vertical bipolar junction transistor (BJT) has a base contact(contact to the first portion 54 a of the epitaxial base region 54 a) onone side of the BJT, whereas the opposing side of the BJT is free tomeasure the potential of the solution, which may be a flowing solution,that is present in the sample trench 300. The device configurationdepicted in FIGS. 1 and 2, allows for the elimination of referenceelectrodes, as used in prior designs. This provides an advantage becauseintegration of reference electrodes on semiconductor chips, such assilicon chips, can be difficult. Further, reference electrodes degradewith use, and therefore can have reliability issues.

The sensing measurement of a sample within the sample trench 300 will bemade as follows. Emitter voltage will be ramped or held at constant. Forexample, the voltage applied to the emitter 36 through the emittercontact 83 will be ramped or held at a constant value of 1 volt or less(<|1|V). The collector voltage will be set to 0. For example, thevoltage applied to the collector 68 through the collector contact 86 canbe set to 0. The base terminal can be set at a fixed voltage, and thebase current flows through it. For example, the voltage applied to thebase, applied to the first portion 54 a of the extrinsic base region,through the base contact 84 can be set at a fixed value, e.g., set at afixed voltage of 1 volt or less (<|1|V), and the base current will flowthrough it. The presence of the base contact eliminates the need for areference electrode. The charges bound to the oxide layer on top of thebase can capacitively couple the base, and modulate the sensingcollector current.

FIGS. 1 and 2 depict a sensor including an exemplary single columncompound semiconductor bipolar junction transistor (BJT) on asemiconductor surface 32, such as a III-V semiconductor substrate or atype IV semiconductor substrate. The term “bipolar junction transistor(BJT)” denotes is a semiconductor device formed by two P-N junctionswhose function is amplification of an electric current. Bipolartransistors are made from 3 sections of semiconductor material, i.e.,alternating P-type and N-type conductivity semiconductor materials, withtwo resulting P-N junctions. As will be described in greater detailbelow the (BJT) devices disclosed herein are vertical bipolar junctiontransistors (VBJT). The term “vertical” as used to describe a BJT devicedenotes that means that the dimension extending from the beginning ofthe emitter 36 through the base 48 to the collector 68 is verticallyorientated or is perpendicular relative to the upper surface of thesubstrate 32. The term “III-V semiconductor” denotes a semiconductormaterial that includes at least one element from Group III of thePeriodic Table of Elements and at least one element from Group V of thePeriodic Table of Elements. Typically, the III-V compound semiconductorsare binary, ternary or quaternary alloys including III/V elements. Incontrast to type III-V semiconductor materials, by “type IVsemiconductor” it is meant that the semiconductor material includes atleast one element from Group IVA (i.e., Group 14) of the Periodic Tableof Elements.

In some embodiments, the bipolar junction transistor containing sensorincludes a vertically oriented stack of an emitter 36 overlying asupporting substrate 32, a base region 48 present directly atop theemitter 36 and a collector 68 atop the base region 48. The base region48 is the region of the device that is present between the emitter 36and the collector 68 of a transistor and into which minority carriersare injected. The collector 68 is a region of the transistor throughwhich a primary flow of charge carriers leaves the base 48. In someembodiments, the emitter 36 is a region from which charge carriers thatare minority carriers in the base are injected into the base.

Each of the emitter 36, the base 48 and the collector 68 may be composedof a semiconductor material, such as a type III-V semiconductormaterial, e.g., InGaAs and/or InGaAlAs, or a type IV semiconductormaterial, such as silicon. The emitter 36 and the collector 68 have adopant conductivity, e.g., n-type that is opposite the conductivity typeof the base region, e.g., p-type. In one example, the collector 68 iscomposed of large grain polycrystalline silicon having a n-typeconductivity, the base 48 is composed of InGaAs and/or InGaAlAs having ap-type conductivity, and the emitter 36 is composed of InGaAs and/orInGaAlAs having an n-type conductivity. It is noted that in someinstances a silicon or silicon germanium material may be substituted forthe aforementioned type III-V semiconductor materials that are providedfor the emitter region and the base region.

The extrinsic base region having the first and second portions 54 a, 54b is typically composed of a same conductivity type dopant as the baseregion 48, but the conductivity type dopant in the first and secondportions 54 a, 54 b of the extrinsic base region is present in a higherconcentration than the concentration type dopant in the base region 48.Similar to the emitter 36, the base 48 and the collector 68, theextrinsic base region 54 a, 54 b may be composed of a semiconductormaterial, such as a type III-V semiconductor material, e.g., InGaAsand/or InGaAlAs, or a type IV semiconductor material, such as silicon.In one example, the extrinsic base region 54 a, 54 b may be composed oflarge grain polysilicon having a p-type conductivity.

The emitter-collector distance is the height of the physical base region48. The height of the physical base region 48 consists of three regions:(i) a space-charge region of the emitter-base diode, (ii) a space-chargeregion of the collector-base diode, and (iii) a quasi-neutral baseregion sandwiched between the two space-charge regions. In someembodiments, it is the quasi-neutral base region that controls thecurrent flow from emitter to the collector, and the height (base width)and doping concentration of the quasi-neutral base region thatdetermined the magnitude of the collector current for a given emitterbase bias voltage. As an example, for a base doping concentration of5×10¹⁸ cm⁻³, and a target width of 20 nm for the quasi-neutral baseregion, the emitter-collector distance should be about 55 nm.

In some embodiment, a first portion of the extrinsic base region 54 a isin contact with a first sidewall of a vertically oriented base region48. The first portion of the extrinsic base region 54 a is electricallycontacted to provide the bias current of the bipolar junction transistorduring sensor operation. The bias current is applied to the firstportion of the extrinsic base region 54 a through a base contact 84. Insome embodiments, a second extrinsic base region 54 b is in contact witha second sidewall of the vertically orientated base region 48. Thesecond portion of the extrinsic base region 54 b includes a sensingelement 200. The sensing element 200 provides the sidewall of the sampletrench 300 that is adjacent to the BJT sensor.

As noted above, the sensing element 200 extends along an entire heightH1 of the second portion of the extrinsic base region 54 b. Thecomposition of the sensing element 200 may be selected for theapplication of the sensor. For example, in one embodiment, the sensingelement is a titanium nitride (TiN) layer, in which the sensing element200 is for sensing pH of a sample within the sample trench 300. Inanother example, the sensing element 200 is composed of a silverchloride (AgCl) layer, in which the sensing element 200 is for sensingchloride (Cl) content of a sample within the sample trench 300. In yetanother example, the sensing element 200 is composed of gold (Au). Asensing element that is provided by a gold (Au) layer may be used forsensing DNA, as well as proteins using this chemistry.

Still referring to FIGS. 1-2, the BJT sensor also includes a pluralityof dielectric layers. For example, a bottom spacer 38 a may separate thefirst and second portions of the extrinsic base region 54 a, 54 b fromthe emitter 36. An upper spacer 38 b may separate the collector 68 fromthe first and second portions of the extrinsic base region 54 a, 54 b. Acollector level dielectric 42 may be present atop the upper spacer 38 b,and the collector level dielectric 42 may have an upper surface that iscoplanar with the upper surface of the collector region 68. In oneembodiment, the collector level dielectric 42 is composed of siliconoxide (SiO₂). An interlevel dielectric layer (ILD) 62 is present atopthe BJT.

The sample trench 300 is formed through the interlevel dielectric layer62, in which a first sidewall S1 of the sample trench 300 includes aportion of the sensing surface 200 (also referred to as sensing surfacelayer), and a second sidewall S2 of the sample trench 300 is entirelyprovided by the interlevel dielectric layer (ILD) 62. Referring to FIG.1, the sensing surface 200 provides the lower portion of the firstsidewall S1 of the sample trench 300, while the upper portion of thefirst sidewall S1 of the sample trench 300 is provided by a portion ofthe interlevel dielectric layer (ILD) 62. The portion of the interleveldielectric layer (ILD) 62 and the sensing surface 200 that provides thefirst sidewall S1 of the sample trench 300 are aligned to one another.

In some embodiments, contacts 83, 84, 86 are formed through the ILDlayer 62 and the collector level dielectric 42. An emitter contact 83may be present within a via extending through the interlevel dielectriclayer 62 and the lower spacer 38 a to provide that the emitter contact83 is in direct contact with the emitter layer 36. A base contact 84 maybe present within a via extending through the interlevel dielectriclayer 62, the collector level dielectric 42, and the upper spacer layer38 b to provide that the base contact 84 is in direct contact with thefirst portion of the extrinsic base region 54 a. A collector contact 86may extend through the interlevel dielectric layer 62 into directcontact with the collector 68.

Referring to FIGS. 1 and 2, the sample trench 300 is positioned forhorizontal sensing. In the embodiment that is depicted in FIGS. 1 and 2,the sensing BJT is present on one side of the sample trench 300. FIG. 2is a down view of a BJT sensor including a horizontally positionedsample trench 300 and a single BJT having a single sensing surface 200providing a sidewall of the sample trench 300. The direction of flow ofthe sample 350 being sensed within the sample trench 300 is identifiedby the arrow. The width W1 of the sample trench 300 may be selected inaccordance with the sample from which the measurements are being taken.For example, some DNA molecules within the sample 350 may have a maximumdimension (i.e., largest dimension characterizing a single DNAmolecule), e.g., length or diameter, that is 3 Å. Some small proteinsthat may be sensed from the sample 350 may have a maximum dimension(i.e., largest dimension characterizing a single protein), e.g.,diameter, ranging from 50 Å to 100 Å. Some enzymes that can be sensedfrom the sample 350 within the sample trench 300 of the BJT sensor canhave a maximum dimension (i.e., largest dimension characterizing asingle DNA molecule), e.g., length or diameter, that is 400Λ.

The width W1 of the sample trench 300 may be selected to accommodate theabove samples. In other examples, width W1 of the sample trench 300 maybe as great as 5 microns for analyzing cancer cells. In yet otherexamples, the width W1 of the sample trench 300 may be as great as 100nm for analyzing large proteins.

It is noted that the embodiment depicted above with reference to FIGS. 1and 2 that includes a single BJT device on one side of the sample trench300 is only one example of a sensor in accordance with the methods andstructures disclosed herein. In other embodiments, two BJTs of oppositepolarity, i.e., opposite conductivity type, can be employed as a sensor,in which each BJT includes a sensing surface that provides a sidewall ofa sample trench 300. For example, a first BJT being be a NPN device on afirst side of the sample trench 300, and a second BJT being PNP on anopposing side of the sample trench 300. The sample trench 300 isoverlying a shallow trench isolation (STI) region 600. The shallowtrench isolation (STI) region 600 may be composed of an oxide, such assilicon oxide (SiO₂), and provides for isolation of the first verticallyoriented bipolar junction transistor 400 from the second verticallyorientated bipolar junction transistor 500.

FIG. 3 depicts one embodiment of a sensor that includes a sample trench300 and a first and second vertically oriented bipolar junctiontransistor 400, 500. The first vertically oriented bipolar junctiontransistor 400 may be an NPN transistor, and has been described abovewith reference to FIGS. 1 and 2. Each of the reference numbersdesignating structures in the first vertically oriented bipolar junctiontransistor 400 have been described above in the description ofstructures having the same reference numbers with reference to FIGS. 1and 2.

The second vertically oriented bipolar junction transistor 500 issimilar to the first vertically oriented bipolar junction transistor 400that is described with reference to FIGS. 1 and 2. For example, theemitter layer 536 that is depicted in FIG. 3 is similar to the emitterlayer 36 depicted in FIG. 1. The emitter layer 36 depicted in FIG. 3 hasan n-type conductivity for a first vertically oriented bipolar junctiontransistor 400 that is an NPN device, and the emitter layer 536 depictedin FIG. 3 has a p-type conductivity for the second vertically orientedbipolar junction transistor 500 that is a PNP device. Because of thep-type conductivity type of the emitter 536 for the second verticallyoriented bipolar junction transistor 500, the underlying punch throughstop layer/isolation layer 534 is doped to an n-type conductivity. Thevertically oriented base 548 and the collector 568 of the secondvertically oriented bipolar junction transistor 500 are also similar tothe vertically oriented base 48 and the collector 68 that have beendescribed above with reference to FIG. 1. The vertically oriented baseregion 48 depicted in FIG. 3 has a p-type conductivity for a firstvertically oriented bipolar junction transistor 400 that is an NPNdevice, and the vertically oriented base region 548 depicted in FIG. 3has an n-type conductivity for the second vertically oriented bipolarjunction transistor 500 that is a PNP device. The collector region 68depicted in FIG. 3 has an n-type conductivity for a first verticallyoriented bipolar junction transistor 400 that is an NPN device, and thecollector 568 depicted in FIG. 3 has a p-type conductivity for thesecond vertically oriented bipolar junction transistor 500 that is a PNPdevice.

The first vertically oriented bipolar junction transistor 400 includesan extrinsic base region that includes two components. A first portion54 a of the extrinsic base of the first vertically oriented bipolarjunction transistor 400 is physically separate from a second portion 54b of the extrinsic base, and hence are not electrically connected.Similarly, the first portion 554 a of the extrinsic base of the secondvertically oriented bipolar junction transistor 500 is similarlyseparate from the second portion 554 b of the extrinsic base of thesecond vertically oriented bipolar junction transistor 500. The firstportion 54 a, 554 a of the extrinsic base region, i.e., base contact,for each of the first and second vertically oriented bipolar junctiontransistors 400, 500 can be used to set the bias current of thosetransistor during sensing operations. The second portion 54 b, 554 b ofthe extrinsic base portion for each of the vertically oriented bipolarjunction transistors 400, 500 that is adjacent to the sample trench 300,has a sensing surface 200, 201. The sensing surface 200, 201 for each ofthe second portions 54 b, 554 b of the extrinsic base region for thefirst and second vertically oriented bipolar junction transistors 400,500 may extend along an entire height H1 of the extrinsic base 54 b, 554b. The sensing surface 200, 201 extends continuously along the entireheight H1 of the extrinsic base 54 b, 554 b and can have a uniform widthwithout any breaks in continuity.

In the embodiment depicted in FIG. 3, the sensing surface 200, 201 ofthe first and second vertically oriented bipolar junction transistors400, 500 provides the opposing sidewalls of the sample trench 300, inwhich the first vertically oriented bipolar junction transistor 400 ispositioned on one side of the sample trench 300, and the secondvertically oriented bipolar junction transistor 500 is positioned on asecond opposing side of the sample trench 300.

Each of the first sensing surface 200 and the second sensing surface 201may have a composition selected from titanium nitride (TiN), silverchloride (AgCl), gold (Au) and combinations thereof. The application forthe aforementioned compositions, i.e., what the compositions can sensefrom a sample 350 within the sample trench 300, have been describedabove with reference to FIGS. 1 and 2.

Referring back to FIG. 3, the first and second vertically orientedbipolar junction transistors 400, 500 may further include a plurality ofdielectric layers, such as interlevel dielectric layers 62, 562 andcollector level dielectrics 42, 542 that are present on opposing sidesof the sample trench 300. Each of the first and second verticallyoriented bipolar junction transistors 400, 500 include a plurality ofcontacts 83, 84, 86, 583, 584, 586. Referring to FIGS. 3 and 4, thefirst vertically oriented bipolar junction transistor 400 may include anemitter contact 83, a base contact 84 and a collector contact 86.Referring to FIGS. 3 and 4, the second vertically oriented bipolarjunction transistor 500 may include an emitter contact 583, a basecontact 584 and a collector contact 586.

It is noted that in some embodiments, it is not necessary that the firstvertically oriented bipolar junction transistor 400 and the secondvertically oriented bipolar junction transistor 500 have differentconductivity types, i.e., different polarities. For example, in someembodiments both the first vertically oriented bipolar junctiontransistor 400 and the second vertically oriented bipolar junctiontransistor 500 can be NPN transistors. In another example, both thefirst vertically oriented bipolar junction transistor 400 and the secondvertically oriented bipolar junction transistor 500 can be PNPtransistors.

It is also noted that it is not required that a multiple BJT sensor beonly limited to two BJT devices, as depicted in FIGS. 3 and 4. FIG. 5illustrates one embodiment of a sensor including multiple BJT devices700 a, 700 b, 700 c, 700 d, 700 e, 700 f sensing along a single sampletrench 300. Each of the BJT devices 700 a, 700 b, 700 c, 700 d, 700 e,700 f that are depicted in FIG. 5 may be provided by one of the firstand second vertically oriented bipolar junction transistors 400, 500that have been described above with reference to FIGS. 1-4, and includea sensing surface 200, 201 that provides a portion of the sidewall ofthe sample trench 300.

FIG. 6 depicts another embodiment of the present disclosure, whichincludes a sensor for parallel sensing of a sample within a samplereservoir 301 using multiple BJT devices 800 a, 800 b, 800 c, 800 d, 800e, 800 f sensing along a single sample trench 300 a, 300 b, 300 c. Eachof the BJT devices 800 a, 800 b, 800 c, 800 d, 800 e, 800 f that aredepicted in FIG. 6 may be provided by one of the first and secondvertically oriented bipolar junction transistors 400, 500 that have beendescribed above with reference to FIGS. 1-4, and include a sensingsurface 200, 201 that provides a portion of the sidewall of the sampletrench 300 a, 300 b, 300 d. In the embodiment depicted in FIG. 6, thesample reservoir 301 is pumped by micro-pumps 302 into three sampletrenches 300 a, 300 b, 300 c.

The structures depicted in FIGS. 1-6 are now described with greaterdetail with reference to FIGS. 7-19. It is noted that the processsequence depicted in FIGS. 7-19 can provide the structure depicted inFIGS. 1-2. The process sequence depicted in FIGS. 7-19 can also providethe structures depicted in FIGS. 3-6 using hard masks to independentlyprocess the different regions of a substrate, in which BJT devices andsample trenches are formed in accordance with the method described withreference to FIGS. 7-19.

With reference now to FIG. 7, in some embodiments the BJT sensor isformed from a multi-layer structure includes a semiconductor substrate32, such as a type III-V semiconductor substrate or type IVsemiconductor substrate; a relatively wide bandgap semi-isolation layer34; a heavily doped semiconductor layer 36, such as a heavily dopedIII-V semiconductor layer and/or a heavily doped type IV semiconductor,that may later function as a BJT emitter; bottom and top spacers 38 a,38 b, a sacrificial layer 40 between the spacers, and a dielectric (e.g.oxide) layer 42 on the top spacer. In some embodiments, the substrate 32has a surface portion of III-V compound semiconductor material thatallows the subsequent epitaxial growth of III-V compound semiconductormaterials thereon without the difficulties and problems associated withgrowing such material on substrates where a significant lattice mismatchwould be present. The substrate 32 may alternatively comprise a relaxedIII-V layer on a silicon wafer. In an exemplary embodiment, the III-Vmaterial comprising the substrate is InP. In yet another embodiment, thesubstrate 32 may be a type IV semiconductor, such as silicon (Si).

The layer 34 of semi-insulating material is epitaxially grown on thesubstrate 32. The terms “epitaxially growing and/or depositing” and“epitaxially grown and/or deposited” mean the growth of a semiconductormaterial on a deposition surface of a semiconductor material, in whichthe semiconductor material being grown has the same crystallinecharacteristics as the semiconductor material of the deposition surface.In an epitaxial deposition process, the chemical reactants provided bythe source gases are controlled and the system parameters are set sothat the depositing atoms arrive at the deposition surface of thesemiconductor substrate with sufficient energy to move around on thesurface and orient themselves to the crystal arrangement of the atoms ofthe deposition surface. Therefore, an epitaxial semiconductor materialhas the same crystalline characteristics as the deposition surface onwhich it is formed. In an exemplary embodiment using an InP substrate,the semi-isolating layer consists essentially of InAlAs.

The heavily doped III-V compound semiconductor layer 36 is epitaxiallygrown on the semi-isolating layer 34. The lattice constants ofIn_(0.53)Ga_(0.47)As, InAlAs (In_(0.52)Al_(0.48)As), and InP aresubstantially the same, allowing a high quality InGaAs layer to be grownon an InAlAs layer. The bandgap of InAlAs is substantially greater thanthe bandgap of InGaAs and is therefore capable of providing electricalisolation. The dopants in the semiconductor layer 36 may be incorporatedin situ using appropriate precursors, as known in the art. In oneexemplary embodiment, the heavily doped InGaAs layer has a dopingconcentration of 1e19-3e20 cm⁻³ or greater and n-type conductivity. Asused herein, the term “conductivity type” denotes a dopant region beingp-type or n-type. As used herein, “p-type” refers to the addition ofimpurities to an intrinsic semiconductor that creates deficiencies ofvalence electrons. In a silicon-containing substrate, examples of p-typedopants, i.e., impurities include but are not limited to: boron,aluminium, gallium and indium. As used herein, “n-type” refers to theaddition of impurities that contributes free electrons to an intrinsicsemiconductor. Silicon can be used as an n-type or p-type dopant inIII-V semiconductor materials. Other n-type dopants that can be used inIII-V semiconductor materials include tellurium, tin and germanium whileother p-type dopants include zinc and carbon. The thickness of theheavily doped III-V layer 36 may be in the range of 5 nm to 40 nm. Alarger bandgap III-V compound semiconductor material (e.g. GaAs) can beemployed for high voltage or power transistor applications. In anexemplary embodiment in which a heterojunction bipolar transistor isformed, the semiconductor layer 36 could consist essentially of InGaAlAsand function as an emitter. The inclusion of a small percentage ofaluminium (Al) widens the bandgap. The percentage of indium (In) in theemitter of the heterojunction device can be a few percent higher than inthe subsequently formed III-V base layer to compensate for latticeshrinkage due to the smaller size of the aluminium atom.

III-V compound semiconductors are obtained by combining group IIIelements (for example, Al, Ga, In) with group V elements (for example,N, P, As, Sb). GaAs, InGaAs, InP, GaP, and GaN are examples of III-Vcompound semiconductors. Many different III-V compounds could be grownon the substrate 32 and accordingly multiple precursors could be used.Depending on which III-V material(s) is to be grown and which precursoris used, different parameters (temperature, process pressure, times,etc.) are applicable. Metalorganic precursors include Trimethylgallium,Trimethylaluminum, Trimethylindium, Trimethylantimony,Tertiarybutylarsine and Tertiarybutylphosphine. Alternate Group Vprecursors include arsine and phosphine. Depending which Group V sourceis used, process temperature, gas flow, pressure and times varysignificantly. The process parameters for growing III-V semiconductormaterials on silicon and on other III-V semiconductor materials are wellknown in the art and new methods continue to be developed.

The bottom and top spacers 38 a, 38 b may be silicon nitride spacers.The bottom spacer 38 a is deposited as a blanket layer on the dopedepitaxial III-V layer 36. “Blanket” deposition refers to the depositionof the layer without masking of the underlying substrate material. Thespacers can be deposited using directional deposition techniquesincluding, but not necessarily limited to high density plasma (HDP)deposition and gas cluster ion beam (GCIB) deposition, or depositiontechniques including, but not limited to, chemical vapor deposition(CVD), plasma enhanced CVD (PECVD), radio-frequency CVD (RFCVD),physical vapor deposition (PVD), atomic layer deposition (ALD),molecular layer deposition (MLD), molecular beam deposition (MBD),pulsed laser deposition (PLD), liquid source misted chemical deposition(LSMCD), and/or sputtering.

The sacrificial layer 40 deposited on the bottom spacer 38 a may be anamorphous silicon (a-Si) or a polycrystalline silicon (polysilicon)layer that can be etched selectively to the spacer material. Thesacrificial layer material may be deposited by a deposition process suchas, but not limited to, physical vapor deposition (PVD), chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),inductively coupled plasma chemical vapor deposition (ICP CVD), or anycombination thereof. Hydrogenated amorphous silicon is typicallydeposited by plasma-enhanced chemical vapor deposition (PECVD) althoughother techniques such as hot-wire chemical vapor deposition (HWCVD) maybe used. The top spacer 38 b is deposited on the top surface of thesacrificial layer 40.

The oxide layer 42 is deposited on the top surface of the top spacer 38b. Non-limiting examples of materials for the oxide layer 42 includesilicon dioxide, tetraethylorthosilicate (TEOS) oxide, high aspect ratioplasma (HARP) oxide, high temperature oxide (HTO), high density plasma(HDP) oxide, oxides (e.g., silicon oxides) formed by an atomic layerdeposition (ALD) process, or any combination thereof. The oxide layer 42has a thickness in a range from about one hundred to one thousandnanometers in some embodiments, though such a thickness range is notconsidered critical.

As shown in FIG. 8, a trench 44 is formed in the structure depicted inFIG. 7. The etch process used to form the trench 44 may be, for example,a reactive ion etch (RIE) such that the trench includes substantiallyvertical side walls. Sequential RIE processes are employed to etchthrough the oxide layer 42, the top spacer 38 b, and the sacrificiallayer 40, respectively. The bottom spacer 38 a functions as an etch stopfollowing etching of the sacrificial layer 40. The trench 36 accordinglyextends from the top surface of the oxide layer to the bottom spacer 38a. A patterned mask (not shown) having an opening corresponding to thetrench location is formed on the top surface of the oxide layer 42 priorto etching the oxide material and the underlying layers. The maskprotects the remainder of the structure. A trench 44 having a widthbetween five and fifty nanometers can be formed in the fabrication of abipolar junction transistor as described further herein.

A thin oxide liner 46 is formed on the exposed surfaces of thesacrificial layer 40 within the trench. The oxidation may be performedby a plasma oxidation process or other oxidation process that forms athin oxide layer thereon. The resulting structure is schematicallyillustrated in FIG. 8. Following such oxidation, the trench 44 isextended through the bottom spacer 38 a to the doped III-V compoundsemiconductor layer 36.

Referring to FIG. 9, a BJT base material 48 is epitaxially grown on theexposed surface of the doped III-V compound semiconductor layer 36within the trench 44. The base material is lattice-matched to the dopedIII-V compound semiconductor layer 36 or close to lattice-matching. Inthe latter case, a strained base may be obtained. The deposited basematerial may be doped in situ such that it has p-type conductivity, theopposite conductivity type of the semiconductor layer 36. The dopingconcentration of the base material is between 1e17-1e19 cm⁻³ in theexemplary embodiments. The base material 48 optionally consistsessentially of the same III-V material as the layer 36 on which it isformed in some embodiments, for example InGaAs having the samestoichiometry as the underlying layer. A homojunction bipolar junctiontransistor can be fabricated in such embodiments. A portion of the basematerial (overgrowth) may extend above the top surface of the oxidelayer 42. The structure is polished to remove such overgrowth back tothe top surface of the oxide layer, as shown in FIG. 7. Additional oxidematerial is then deposited and planarized on the structure as shown inFIG. 9, thereby increasing the thickness of the oxide layer 42 such thatit covers the exposed surface of the epitaxial base material.

FIG. 10 depicts removal of a sacrificial material from the structureshown in FIG. 9 to expose sidewalls of the vertically oriented baseregion, i.e., BJT base 48. A hard mask 50, for example a silicon nitridemask, is deposited on the oxide layer 42. The hard mask 50 overlaps thebase region containing the base material 48 on all sides and therebyprotects this region and the surrounding region during subsequentprocessing. The periphery of the oxide layer 42 is exposed. The exposedportion of the oxide layer 42 and the portions of the top spacer 38 band sacrificial layer 40 beneath the exposed portion of the oxide layerare recessed using a sequence of reactive ion etch processes, stoppingnear but not necessarily on the top surface of the bottom spacer 38 a.The last phase of the reactive ion etch may be timed to stop within thesacrificial layer 40.

In some embodiments, the sacrificial layer 40 is removed from thestructure to form a space 52 between the bottom and top spacers 38 a, 38b. A wet etch using hot ammonia can be introduced to selectively removethe sacrificial layer while leaving the spacers 38 a, 38 b and the thinoxide liner 46 substantially intact. The thin oxide liner 46 adjoiningthe base material 48 is then removed to obtain the structure shown inFIG. 10. Such removal can involve using a SiCoNi™ etch, a short HF etch,or any other suitable pre-clean process. A SiCoNi™ etch is aplasma-assisted dry etch process that involves simultaneous exposure ofa substrate to hydrogen, NF₃ and NH₃ plasma by-products.

A doped, extrinsic base 54 is epitaxially grown within the recess 52 onand all around the exposed III-V base material 48 (the epitaxial baseregion of a subsequently formed BJT), thereby obtaining a structure asshown in FIG. 11. The doping concentration of the extrinsic base 54 inone or more embodiments is in the range of 4×10¹⁹ atoms/cm³ to 6×10²¹atoms/cm³. The extrinsic base epitaxy is highly defective due to latticemismatch and/or the imperfect exposed surfaces of the base material 48.Exemplary doped extrinsic base materials in some embodiments includesilicon, silicon germanium, and germanium. The defective epitaxy, ratherthan being single crystalline, includes large single crystals with grainboundaries. The extrinsic base 54 is bounded by the bottom and tophorizontal spacers 38 a, 38 b and extends completely around the III-Vbase material 48 with which it is operatively associated. Large grainpolysilicon having p-type conductivity comprises the extrinsic base 54in an exemplary embodiment where the intrinsic, epitaxial base region isalso p-type. Defects within the extrinsic base 54 will not propagateinto the base epitaxy (base material 48), which is used as a seed layer,upon epitaxial growth of the extrinsic base 54 thereon. Doped poly-SiGe,doped poly-Ge and doped III-V compound semiconductor materials are amongthe materials that may alternatively be employed for the extrinsic base54 of the exemplary structure.

Following formation of the doped, extrinsic base 54, the extrinsic basematerial is recessed using a reactive ion etch. The hard mask 50protects the layers beneath it, including the oxide layer 42, the topspacer 38 b, the base material 48 and a portion of the extrinsic base 54around the base material. The bottom spacer 38 a functions as an etchstop following removal of the selected portion of the extrinsic basematerial.

The extrinsic base 54 is further processed to provide the first andsecond portions 54 a, 54 b, as depicted in FIGS. 1-2. This can includefurther photolithography and etch processes.

Referring to FIG. 12, an interlayer dielectric (ILD) layer 62, forexample silicon dioxide or a low-k dielectric such as SiOCH, is formedon the structure using CVD or other known techniques. The ILD layer 62may be formed from other dielectric materials, including but not limitedto, spin-on-glass, a flowable oxide, a high density plasma oxide,borophosphosilicate glass (BPSG), or any combination thereof. The ILDlayer is deposited by any suitable deposition process, including, butnot limited to CVD, PVD, plasma-enhanced CVD, atomic layer deposition(ALD), evaporation, chemical solution deposition, or like processes. Theouter surfaces of the doped, extrinsic base 54 are protected by the ILDlayer. The ILD layer 62 is planarized using chemical mechanicalplanarization (CMP), as known in the art, down to the top surface of thehard mask 50. The hard mask 50 over the base region is removed and thetop surface is planarized to obtain the structure shown in FIG. 12.

A second hard mask 64 is then deposited and patterned on the top surfaceof the structure depicted in FIG. 12. The second hard mask includes anopening above the base region while protecting other regions of thestructure. Using the second hard mask 64, a recess 66 is formed in thestructure that extends through the oxide layer 42 down to the top spacer38 b. The portion of the III-V base material 48 extending above the topspacer 38 b is also removed. A reactive ion etch (RIE) may be employedto selectively remove the oxide material and the III-V material therein.Etching of the III-V material is timed or otherwise controlled to avoidremoving III-V material beneath the top spacer 38 b. The etch isselective to the top spacer material, which is silicon nitride in theexemplary embodiment.

Referring to FIG. 14, a second (top) heavily doped III-V compoundsemiconductor layer 68 that functions as a BJT collector is epitaxiallygrown on the exposed top surface of the base material 48 and within therecess 66. The dopants in the second semiconductor layer 68 of the BJTmay be incorporated in situ using appropriate precursors, as known inthe art. The epitaxy may be essentially polycrystalline rather thansingle crystal due to surface imperfections of the base material 48 onwhich the semiconductor layer 68 is grown. Defects in the top III-Vcompound semiconductor layer 68 may further arise due to lateral growthalong the top spacer 38 b and along the sidewalls of the oxide layer 42.Defects within the large grain epitaxy will not, however, propagate intothe underlying base epitaxy. In one exemplary embodiment, a heavilydoped polycrystalline InGaAs layer grown on the base material 48 has adoping concentration of 1e¹⁹-3e20 cm⁻³ or greater and n-typeconductivity. The second hard mask 64 is removed and the structure isoptionally planarized to obtain the structure schematically shown inFIG. 14.

In a following process sequence, the sample trench 300 is formedexposing a sidewall of the second portion 54 b of the extrinsic base 54.If not previously formed, ILD material for an ILD layer 62 is depositedon the structure. Thereafter, the sample trench 300 is formed usingphotolithography and etching. Specifically, a pattern is produced byapplying a photoresist to the surface to be etched; exposing thephotoresist to a pattern of radiation; and then developing the patterninto the photoresist utilizing a resist developer. Once the patterningof the photoresist is completed, the sections covered by the photoresistare protected while the exposed regions are removed using a selectiveetching process that removes the unprotected regions. For example, theexposed portions of the ILD layer 62 may be removed with an anisotropicetch, such as reactive ion etching (RIE). The etch process may beselective to the lower spacer level 38 a, and exposes a sidewall of thesecond portion 54 b of the extrinsic base.

FIG. 16 depicting one embodiment of a lateral etch process to laterallyetching the extrinsic base region of the structure depicted in FIG. 15forming an undercut region 308. More specifically, the second portion ofthe extrinsic base region 54 b may be laterally etched by an isotropicetch process that removes the material of the extrinsic base region 54 bselectively to at least the lower spacer layer 38 a, the interleveldielectric layer 62 and the collector level dielectric 42. For example,when the extrinsic base region 54 b is composed of silicon, the lateraletch may be a KOH based wet etch.

FIG. 17 depicts one embodiment of depositing at least one metalcontaining material 309 within the sample trench 300, as well as theundercut region 308. The at least one metal containing material 309 thatis deposited in the undercut region 308 may be composed of titaniumnitride (TiN), gold (Au), silver chloride (AgCl) or other material thatcan provide the sensing surface 200, 201, as described with reference toFIGS. 1-4. The at least one metal containing material 309 may bedeposited using a chemical vapor deposition, e.g., plasma enhancedchemical vapor deposition (PECVD), and/or an atomic layer deposition(ALD) process. For example, a complete metal fill may be provided byatomic layer deposition (ALD) titanium nitride (TiN), or conformal linerdeposition by ALD TiN that is followed by metal fill using chemicalvapor deposition (CVD) titanium nitride (TiN). In some embodiments, anoptional post-deposition annealing process may be applied. In someembodiments, the deposition of the at least one metal containingmaterial 309 is followed by a planarization process to remove any metalmaterial that overburdens/overfills the sample trench 300. In someembodiments, the planarization process is provided by chemicalmechanical planarization (CMP).

FIG. 18 depicts recessing a portion of the metal 309 that is presentwithin the sample trench 300. In some embodiments, the metal 309 isfirst recessed with an isotropic wet etch. For example, when the metal309 is composed of titanium nitride (TiN), the etch process forrecessing the titanium nitride may be an isotropic wet etch that is,e.g., Cl-based, or H₂O₂/NH₄OH-based. The height of the recessed metal309 a may be substantially equal to the height that corresponds to theupper surface of the undercut region 308. It is noted that the aboveetch composition provides only one example of an etch process that maybe employed at this stage of the process flow, and that othercompositions are equally applicable. For example, etch composition foretching gold (Au) or silver chloride (AgCl) may be employed when thesensing surface 200, 201 being formed is composed of gold (Au) or silverchloride (AgCl).

FIG. 19 depicts applying an anisotropic etch process to the recessedmetal 309 a that is present within the sample trench 300. Theanisotropic etch process removes a majority of the metal, while aremainder of the metal is present in the undercut region 308 to providethe sensing element 200, 201 of the BJT sensor. As used herein, an“anisotropic etch process” denotes a material removal process in whichthe etch rate in the direction normal to the surface to be etched isgreater than in the direction parallel to the surface to be etched. Inone embodiment, the anisotropic etch process removes all the metal 309that is present within the sample trench 300 except for the portionwithin the undercut region 308 that is protected by the overlyingportions of the upper spacer layer 38 b, the overlying portions of thecollector level dielectric layer 42, and the overlying portions of theILD 62. Because of the anisotropic nature of the etch process, theremaining portion of the metal present in the undercut region 308 thatprovides the sensing surface 200, 201 and provides a sidewall that isaligned with the first sidewall S1 of the sample trench 300 provided bythe overlying portions of the upper spacer layer 38 b, the overlyingportions of the collector level dielectric layer 42, and the overlyingportions of the ILD 62.

In some embodiments, the anisotropic etch that is employed at this stageof the process flow includes reactive ion etching. Reactive Ion Etching(RIE) is a form of plasma etching in which during etching the surface tobe etched is placed on the RF powered electrode. Moreover, during RIEthe surface to be etched takes on a potential that accelerates theetching species extracted from plasma toward the surface, in which thechemical etching reaction is taking place in the direction normal to thesurface.

In some embodiments, when the recessed metal 309 a is composed oftitanium nitride, the reactive ion etch process may employ Cl-based etchchemistries, such as Ar/Cl₂, or Xe/Cl₂. Other examples of anisotropicetching that can be used at this point of the present invention includeion beam etching, plasma etching or laser ablation.

Referring to FIGS. 1 and 2, the emitter, base and collector contacts 82,84, 86 are the formed. Photolithographic and etching techniques known tothe art may be employed to form trenches within the ILD layer and otherlayers prior to metal deposition. Contact material may, for example,include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium(Ti), palladium (Pd) or any combination thereof. Exemplary processes fordepositing contact material include CVD, PECVD, PVD, plating, thermal ore-beam evaporation, or sputtering. A planarization process, for example,CMP, is performed to remove any electrically conductive material fromthe top surface of the ILD layer.

It is to be appreciated that the various layers and/or regions shown inthe accompanying figures may not be drawn to scale. Furthermore, one ormore layers of a type commonly used in such integrated circuit devicesmay not be explicitly shown in a given figure for ease of explanation.This does not imply that the layer(s) not explicitly shown are omittedin the actual integrated circuit device.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

Having described preferred embodiments of a system and method (which areintended to be illustrative and not limiting), it is noted thatmodifications and variations can be made by persons skilled in the artin light of the above teachings. It is therefore to be understood thatchanges may be made in the particular embodiments disclosed which arewithin the scope of the invention as outlined by the appended claims.Having thus described aspects of the invention, with the details andparticularity required by the patent laws, what is claimed and desiredprotected by Letters Patent is set forth in the appended claims.

The invention claimed is:
 1. A bipolar junction transistor containingsensor comprising: a vertically oriented stack of a collector atop abase region; a first extrinsic base region in contact with a firstsidewall of the base region, wherein the first extrinsic base region iselectrically contacted to provide a bias current of the bipolar junctiontransistor during sensor operation; a second extrinsic base region incontact with a second sidewall of the base region, the second extrinsicbase region including a sensing element; and a sample trench having atrench sidewall provided by the sensing element.
 2. The bipolar junctiontransistor containing sensor of claim 1, wherein the sensing elementthat provides the trench sidewall extends an entire height of the secondextrinsic base region.
 3. The bipolar junction transistor containingsensor of claim 1, wherein the sensing element is a titanium nitridelayer, and the sensing element is for sensing pH of a sample within thesample trench.
 4. The bipolar junction transistor containing sensor ofclaim 1, wherein the sensing element is comprised of silver chloride,and the sensing element is for sensing chloride content of a samplewithin the sample trench.
 5. The bipolar junction transistor containingsensor of claim 1, wherein the sensing element is comprised of gold. 6.A sensor comprising: a sample trench; a first bipolar junctiontransistor doped to a first conductivity type having a first sensingsurface of a first extrinsic base region providing a first sidewall ofthe sample trench; and a second bipolar junction transistor doped to asecond conductivity type having a second sensing surface of a secondextrinsic base region providing a second sidewall of the sample trench.7. The sensor of claim 6, wherein the first conductivity type is n-typeand the second conductivity type is p-type.
 8. The sensor of claim 6,wherein the first sensing surface extends an entire height of the firstextrinsic base region.
 9. The sensor of claim 8, wherein the firstsensing surface has a composition selected from the group consisting oftitanium nitride (TiN), silver chloride (AgCl), gold (Au), andcombinations thereof.
 10. The sensor of claim 6, wherein the secondsensing surface extends an entire height of the second extrinsic baseregion.
 11. The sensor of claim 10, wherein the second sensing surfacehas a composition selected from the group consisting of titanium nitride(TiN), silver chloride (AgCl), gold (Au), and combinations thereof. 12.A method of forming a sensor comprising: forming a bipolar junctiontransistor including a base region, and a two-component extrinsic baseregion; forming a sample trench exposing a sidewall of a first componentof the two-component extrinsic base region; and forming a sensor surfaceon the sidewall of the first component of the extrinsic base region thatis opposite a sidewall of the first component of the extrinsic baseregion that is in contact with the base region.
 13. The method of claim12, wherein said forming the sample trench comprises depositing at leastone dielectric layer on the bipolar junction transistor, and etching thesample trench into the at least one dielectric layer.
 14. The method ofclaim 13, wherein said forming the sensor surface on the sidewall of thefirst component of the extrinsic base region comprises applying alateral etch to the sidewall of the first component of the extrinsicbase region to form an undercut region present underlying the at leastone dielectric layer; and filling the undercut region with a themetal-containing material.
 15. The method of claim 14, wherein themetal-containing material that provides the sensor surface is selectedfrom the group consisting of titanium nitride (TiN), silver chloride(AgCl), gold (Au) and combinations thereof.
 16. The method of claim 14,wherein said filling the undercut region comprises atomic layerdeposition (ALD) of the metal-containing material.
 17. The method ofclaim 16, wherein following said filling the undercut region, and etchprocess removes the metal-containing material that overfills theundercut region.
 18. The method of claim 17, wherein the etch processthat removes the metal-containing material that overfills the undercutregion is an anisotropic etch.
 19. The method of claim 18, wherein theanisotropic etch is reactive ion etching.
 20. The method of claim 18,wherein a second component of the two-component extrinsic base regionthat is separate from the first component of the two-component extrinsicbase region is electrically contacted to provide a bias current of thebipolar junction transistor during sensor operation.